1. Field of the Invention
The present invention relates to an information processing apparatus, a buffer control method, and a computer program.
2. Description of the Related Art
An image pickup apparatus, such as a digital steel camera, generally uses a solid-state image pickup device such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor) imager as an image pickup device. In particular, the CMOS imager can read out data at high speed and is suited for realization of real-time processing which demands high-speed performance.
When image data is read into a camera system LSI from a front end and image processing is performed, the image data output from the front end is first output to a camera signal processor and is subjected to various camera signal processing. At this time, the same image data is also output from the front end to an image signal detector for performing processing on detected signals of the image photographed by the camera. The image data processed by the camera signal processor is output to a data bus by a memory controller and to an image memory via a memory interface (also referred to as “memory I/F” hereinafter) and is temporarily stored therein. The image data temporarily stored in the image memory is output from the image memory to the data bus via the memory I/F again by the memory controller. After that, the image data is input into a memory interface (also referred to as “monitor I/F” hereinafter) for display or to an image compressor/decompressor, and then subjected to a processing for outputting it to an external monitor and to a recording process, after a predetermined image processing is performed thereon.
When such flow of data is practiced, the data bus is shared by a plurality of image processing blocks, and hence it is necessary to pay attention to the usage of data bus bandwidth. In particular, when the image data is read out from the CMOS imager at high speed and temporarily stored in the image memory in order to realize real-time processing which demands high-speed performance, there is concern that the usage of data bus bandwidth may substantially increase instantaneously. Under such circumstances, other image processing blocks or a microcomputer cannot use the data bus, which therefore reduces processing efficiency. Moreover, instantaneous and substantial increase in the usage of data bus bandwidth leads to an increase in the peak value of power consumption within the LSI, and hence stable operation may not be ensured from the aspect of power supply.
In order to overcome such difficulties, there is disclosed in Japanese Unexamined Patent Application Publication No. 2002-135663 a means for inserting a FIFO data buffer in between an external input part and a data processor, receiving input data temporarily by the FIFO data buffer, and controlling output rate from the buffer. With such method, it is possible to compare the remaining amount of data in the FIFO data buffer with the amount of the input data, to determine increase or decrease of output data rate corresponding to this comparison result, and to transmit data in a phased manner, which is therefore effective for data rate control.
Moreover, there is disclosed in Japanese Unexamined Patent Application Publication No. H10-322571 a method for performing input image data processing necessary for camera signal processing by the common line buffer control with image processing, by sharing a line memory for the image processing and simultaneously performing mirror reverse processing of the input image data.